Therefore, a bit synchronization algorithm is necessary to obtain bit edges and NH code phases. Han, Zhifeng Liu, Jianye Li, Rongbing Zeng, Qinghua Wang, YiīeiDou system navigation messages are modulated with a secondary NH (Neumann-Hoffman) code of 1 kbps, where frequent bit transitions limit the coherent integration time to 1 millisecond. (semiconductor integrated circuits)Ī Modified Differential Coherent Bit Synchronization Algorithm for BeiDou Weak Signals with Large Frequency Deviation. With a 4.9 MHz sine wave input, the prototype ADC implemented in a 0.18-, demonstrates a maximum signal-to-noise distortion ratio (SNDR) and SFDR of 66.32 and 83.38 dB, respectively, at a 4.9 MHz analog input and a power consumption of 102 mW from a 1.8 V supply. This paper describes a 12- bit 40 MS/s calibration-free pipelined analog-to-digital converter (ADC), which is optimized for high spurious free dynamic range (SFDR) performance and low power dissipation. Wei Qi Yin Xiumei Han Dandan Yang Huazhong, E-mail: [Department of Electronic Engineering, Tsinghua University, Beijing 100084 (China) A 12- bit 40 MS/s pipelined ADC with over 80 dB SFDRĮnergy Technology Data Exchange (ETDEWEB)
0 Comments
Leave a Reply. |